Page 1275 - 5G Basics - Core Network Aspects

Transport aspects 2

E.4.2 Errors detected by mapper

Errors encountered before the mapper, such as loss of client signal on any physical lane of the interface,
will result in the insertion of an Ethernet LF sequence ordered set prior to this process. The same action
should be taken as a result of failure to achieve 66B block lock on any PCS lane, failure to achieve lane
alignment marker framing on each PCS lane, or failure to de-skew because the skew exceeds the buffer
available for de-skew.

An invalid 66B block will be converted to an error control block before transcoding. An invalid 66B block is
one which does not have a sync header of "01" or "10", or one which has a sync header of "10", is not a
valid PCS lane alignment marker and has a control block type field which does not appear in Figure B.2 or
has one of the values 0x2d, 0x33, 0x66, or 0x55 which are not used for 40GBASE-R or 100GBASE-R. An error
control block has sync bits of "10", a block type code of 0x1e, and 8 seven-bit/E/error control characters.
This will prevent the Ethernet receiver from interpreting a sequence of bits containing this error as a valid
packet.

E.4.3 Errors detected by de-mapper
Several mechanisms will be employed to reduce the probability that the de-mapper constructs erroneous
parallel 64B/66B encoded data at the egress if bit errors have corrupted. Since detectable corruption
normally means that the proper order of 66B blocks to construct at the de-mapper cannot be reliably
determined, if any of these checks fail, the de-mapper will transmit eight 66B error control blocks
(sync="10", control block type=0x1e, and eight 7-bit/E/control characters).
Mechanisms for improving the robustness and for 513B block lock including PCS lane alignment markers
are discussed in Annex F.

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