Page 1270 - 5G Basics - Core Network Aspects

2 Transport aspects

Annex E

Adaptation of parallel 64B/66B encoded clients
(This annex forms an integral part of this Recommendation.)

E.1 Introduction
IEEE 40GBASE-R and 100GBASE-R interfaces specified in [IEEE 802.3] are parallel interfaces intended for
short-reach (up to 40 km) interconnection of Ethernet equipment. This annex describes the process of
converting the parallel format of these interfaces into a serial bit stream to be carried over the OTN.
The order of transmission of information in all the diagrams in this annex is first from left to right and then
from top to bottom.

E.2 Clients signal format
40GBASE-R and 100GBASE-R clients are initially parallel interfaces, but in the future they may be serial
interfaces. Independent of whether these interfaces are parallel or serial, or what the parallel interface lane
count is, 40GBASE-R signals are comprised of four PCS lanes, and 100GBASE-R signals are comprised of
twenty PCS lanes. If the number of physical lanes on the interface is fewer than the number of PCS lanes,
the appropriate number of PCS lanes is bit-multiplexed onto each physical lane of the interface. Each PCS
lane consists of 64B/66B encoded data with a PCS lane alignment marker inserted on each lane once per
16384 66-bit blocks. The PCS lane alignment marker itself is a special format 66B codeword.

The use of this adaptation for 40GBASE-R into OPU3 also applies the transcoding method that appears in
Annex B and the framing method of Annex F. The adaptation described in this annex alone can be used for
the adaptation of 100GBASE-R into OPU4.

E.3 Client frame recovery

Client framing recovery consists of the following:
 bit-disinterleave the PCS lanes, if necessary. This is necessary whenever the number of PCS lanes
and the number of physical lanes is not equal, and is not necessary when they are equal (e.g., a 4-
lane 40GBASE-R interface);
 recover 64B/66B block lock as per the state diagram in Figure 82-10 of [IEEE 802.3];

 recover lane alignment marker framing on each PCS lane as per the state diagram in Figure 82-11
of [IEEE 802.3];

 reorder and de-skew the PCS lanes into a serialized stream of 66B blocks (including lane alignment
markers). Figure E.1 illustrates the ordering of 66B blocks after the completion of this process for
an interface with p PCS lanes.

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