Page 1277 - 5G Basics - Core Network Aspects

Transport aspects 2

At the de-mapper, invalid flag bit parity will cause both of the 513B blocks across which the flag bit parity
applies to be decoded as 8  2 66B error control blocks ("10" sync header, control block type 0x1e, followed
by eight 7-bit/E/control characters).

F.3 66B block sequence check
Bit error corruption of the position or flag continuation bits could cause 66B blocks to be de-mapped from
513B code blocks in the incorrect order. Additional checks are performed to prevent that this results in
incorrect packet delineation. Since detectable corruption normally means that the proper order of 66B
blocks to construct at the decoder cannot be reliably determined, if any of these checks fail, the decoder
will transmit eight 66B error control blocks (sync="10", control block type=0x1e, and eight 7-bit/E/control
characters).
Other checks are performed to reduce the probability that invalid data is delivered at the egress in the
event that bit errors have corrupted any of the POS fields or flag continuation bits "FC".
If flag bit "F" is 1 (i.e., the 513B block includes at least one 64B/66B control block), for the rows of the table
up until the first one with a flag continuation bit of zero (the last one in the block), it is verified that no two
66B control blocks or lane alignment markers within that 513B block have the same value in the POS field,
and further, that the POS field values for multiple control or lane alignment rows are in ascending order,
which will always be the case for a properly constructed 513B block. If this check fails, the 513B block is
decoded into eight 66B error control blocks.
The next check is to ensure that the block sequence corresponds to well-formed packets, which can be
done according to the state diagram in Figures F.2 and F.3. This check will determine if 66B blocks are in an
order that does not correspond to well-formed packets, e.g., if during an IPG an all-data 66B block is
detected without first seeing a control block representing packet start, or if during a packet a control/idle
block is detected without first seeing a control block representing packet termination, control blocks have
likely been misordered by corruption of either the POS bits or a flag continuation bit. Failure of this check
will cause the 513B block to be decoded as eight 66B error control blocks. Note that PCS lane alignment
markers are accepted in either state and do not change state as shown in Figure F.3.
The sequence of PCS lane alignment markers is also checked at the decoder. For an interface with p PCS
lanes, the PCS lane alignment markers for lanes 0 to p-1 will appear in a sequence, followed by 16383p
non-lane-marker 66B blocks, followed by another group of PCS lane alignment markers. A counter is
maintained at the decoder to keep track of when the next group of lane alignment markers is expected. If,
in the process of decoding lane alignment markers from a 513B block, a lane alignment marker is found in a
position where it is not expected, or a lane alignment marker is missing in a position where it would have
been expected, the entire 513B block is decoded as eight 66B error control blocks as shown in Figures F.2,
F.3, and F.4.

F.3.1 State diagram conventions
The body of this clause is comprised of state diagrams, including the associated definitions of variables,
constants, and functions. Should there be a discrepancy between a state diagram and descriptive text, the
state diagram prevails.
The notation used in the state diagrams follows the conventions of clause 21.5 of [IEEE 802.3]. State
diagram timers follow the conventions of clause 14.2.3.2 of [IEEE 802.3]. The notation ++ after a counter or
integer variable indicates that its value is to be incremented.

F.3.2 State variables

F.3.2.1 Constants
EBLOCK_T<65:0>

66-bit vector to be sent to the PCS containing /E/ in all the eight character locations.

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