Page 203 - Cloud computing: From paradigm to operation
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Framework and requirements for cloud computing                                 1


                                            Table I.4 – ETSI related specifications

                       Specification                             Summary                         Published

             Hardware Interoperability       The document develops a set of normative             2017-03
             Requirements Specification [b-ETSI   interoperability requirements for the NFV hardware
             EVE007]                         ecosystem and telecommunications physical
                                             environment to support NFV deployment.


            I.2     Relationship with related specifications from other SDOs
            Table I.5 analyses the relationship between functional requirement introduced in this Recommendation and
            the related Specification from other SDOs. The major differences between this Recommendation and other
            related Specifications are as follows:

            –       'Monitoring environment condition' (see clause 7.1.6) and 'No additional ports' (see clause 7.5) are
                    not addressed in the specifications identified in I.1
            –       This Recommendation introduced the physical machine with functional requirements derived by
                    use  cases  with  general  purpose;  other  deliverables  from  other  SDOs  are  specific  for  server
                    implementation or interface in detail.


                              Table I.5 – Relationship with related specifications from other SDOs

              NO.     Requirements in this          Relationship with related specifications from other SDOs
                       Recommendation
                1    Virtualization        –  [b-OCP 1S] provides virtualization instruction set as 'The Twin Lakes 1S
                     instruction set          server is designed to use Intel Xeon Processor D-2191 utilizing the
                                              performance and advanced Intelligence of Intel Xeon processors packaged
                                              into a dense, lowpower SoC' in clause 3.
                                           –  [b-OCP BS] provides virtualization instruction set as 'Intel Xeon
                                              Haswell/Broadwell-EP' in clause 2 table 2-1.
                                           –  [b-OCP HSAS] provides virtualization instruction set as 'The motherboard is
                                              designed to support dual Intel Xeon E5-2600 v3 and v4 series processors
                                              and up to 2048GB LRDIMM 3DS/1024GB LRDIMM/ 512GB RDIMM DDR4
                                              memory. Leveraging advanced technology from Intel, the motherboard is
                                              capable of offering scalable 32- and 64- bit computing, high-bandwidth
                                              memory design and lightning-fast PCI-E bus implementation' in clause 7.
                                           –  [b- OCP IMBH] provides virtualization instruction set as 'The Efficiency
                                              Performance motherboard, built with the Intel Xeon E5-2600 processor, was
                                              originally was code-named the Sandy Bridge-EP motherboard' in clause 4.
                                           –  [b-OCP OAPM] provides virtualization instruction set as 'CPU: AMD EPYC
                                              processors' in clause 5.
                                           –  [b-OCP MB] provides virtualization instruction set as 'Intel Motherboard
                                              V3.1 (also referred to "motherboard" or "the motherboard" in this
                                              document, unless noted otherwise) is based on Intel Xeon Processor E5-
                                              2600 v3 (formerly code-named Haswell-EP processor) product family CPU
                                              architecture' in clause 4.1


















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