Page 1282 - 5G Basics - Core Network Aspects

2 Transport aspects

.......
1 3824
1
2
3
4
ODU0

....... ...... ....... ...
1 14 15 239 240 ... 255 14 blocks of 4 (239 + 16) bytes 3826 4064 4065 4080
OTU0LL RS(255,239) RS(255,239)
1 FA OH
OH FEC FEC
RS(255,239) RS(255,239)
2
(4 239 bytes) FEC (4 239 bytes) FEC
3 RS(255,239) RS(255,239)
FEC FEC
RS(255,239) RS(255,239)
4 FEC FEC
OTU0LL G.709-Y.1331(12)-Amd.2(13)_FG.1
Column #
1 2 3 4 5 6 7 8 9 10 11 12 13 14
FAS MFAS SM GCC0 RES

Figure G.1  OTU0LL frame structure, overhead and ODU0 mapping

The transmission order of the bits in the OTU0LL frame is left to right, top to bottom, and MSB to LSB (see
Figure G.2).

Figure G.2  Transmission order of the OTU0LL frame bits

G.2.2 Scrambling
The OTU0LL signal must have sufficient bit timing content at the NNI. A suitable bit pattern, which prevents
a long sequence of "1"s or "0"s, is provided by using a scrambler.
The operation of the scrambler shall be functionally identical to that of a frame synchronous scrambler of
sequence length 65535 operating at the OTU0LL rate.
16
12
3
The generating polynomial shall be 1 + x + x + x + x . Figure G.3 shows a functional diagram of the frame
synchronous scrambler.

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