Page 1300 - 5G Basics - Core Network Aspects

2 Transport aspects

Table VI.2 – Parallel logic equations for the CRC-8 implementation

CRC checksum bits
Mapping
overhead bits crc1 crc2 crc3 crc4 crc5 crc6 crc7 crc8

JC1.C1 X X X
JC1.C2 X X X

JC1.C3 X X X
JC1.C4 X X X
JC1.C5 X X X
JC1.C6 X X X
JC1.C7 X X X
JC1.C8 X X X
JC2.C9 X X X X X
JC2.C10 X X X X X
JC2.C11 X X X X X
JC2.C12 X X X
JC2.C13 X X X
JC2.C14 X X X
JC2.II X X X

JC2.DI X X X
CRC-5

5
Table VI.3 illustrates example logic equations for a parallel implementation of the CRC-5 using the g(x) = x
+ x + 1 polynomial over the JC4-JC5 CnD fields. An "X" in a column of the table indicates that the message bit
of that row is an input to the Exclusive-OR equation for calculating the CRC bit of that row. JC4.D1
corresponds to the first bit (MSB) of the first mapping overhead octet (JC1), JC4.D2 corresponds to bit 2 of
the first mapping overhead octet, etc. After computation, CRC bits crc1 to crc5 are inserted into the JC6
octet with crc1 occupying JC6 bit 4 and crc5 the JC6 bit 8.

Table VI.3 – Parallel logic equations for the CRC-5 implementation

CRC checksum bits
Mapping
overhead bits
crc1 crc2 crc3 crc4 crc5
JC4.D1 X X X
JC4.D2 X X X
JC4.D3 X X
JC4.D4 X X
JC4.D5 X X
JC5.D6 X X X

JC5.D7 X X
JC5.D8 X X
JC5.D9 X X
JC5.D10 X X

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