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Transport aspects                                              2


            The lanes are identified, de-skewed, and reassembled into the original OTU4 frame according to the lane
            marker. The MFAS can be combined with the lane marker to provide additional skew detection range, the
            maximum  being  up  to  the  least  common  multiple  "LCM(240,  256)/2  –  1"  or  1919  OTU4  frame  periods
            (approximately 2.241 ms). In mapping from lanes back to the OTU4 frame, the sixth byte of each OTU4
            frame which was borrowed for lane marking is restored to the value OA2.
            Each  physical  lane  of  an  OTL4.4  carried  over  a  multi-lane  SOTU  interface  is  formed  by  simple  bit
            multiplexing of five logical lanes. At the sink, the bits are disinterleaved into five logical lanes from each
            physical lane. The sink will identify each logical lane according to the lane marker in the LLM byte. The sink
            must be able to accept the logical lanes in any position as the ordering of bit multiplexing on each physical
            lane is arbitrary; the optical module hardware to be used for this application is permitted full flexibility
            concerning which physical lane will be used for output of each logical lane, and the order of bit multiplexing
            of logical lanes on each physical output lane.

            NOTE 4 –  Ten-lane IEEE 100GBASE-R interfaces are  specified, although not with ITU-T physical  layer  specifications.
            These interfaces may be compatible with a 10-lane interface for OTU4 (OTL4.10), each lane consisting of two bit-
            multiplexed logical lanes. Refer to[b-ITU-T G-Sup.58].
            This mechanism handles any normally framed OTU3 or OTU4 sequence.


                                           Rotate            Rotate           Rotate            Rotate
                           MFAS = xxxx xx00     MFAS = xxxx xx01  MFAS = xxxx xx10  MFAS = xxxx xx11
                       1       2        255    256        510    511       765     766       1020    1
                Lane 0 1:16 (FAS)  65:80  16247:16272  49:64  16305:16320  33:48  16289:16304  17:32  16263:16288 1:16 (FAS)
                Lane 1  17:32  81:86  ...  16263:16288 1:16 (FAS)  ...  16247:16272  49:64  ...  16305:16320  33:48  ...  16289:16304  17:32
                Lane 2  33:48  97:112  16289:16304  17:32  16263:16288 1:16 (FAS)  16247:16272  49:64  16305:16320  33:48
                Lane 3  49:64  113:128  16305:16320  33:48  16289:16304  17:32  16263:16288 1:16 (FAS)  16247:16272  49:64
                                                                                             G.709-Y.1331(12)_FC.2


                                 Figure C.2 – Distribution of bytes from OTU3 to parallel lanes

                                            Rotate           Rotate            Rotate           Rotate
                           LLM MOD 20 = 0        LLM MOD 20 = 1   LLM MOD 20 = 18   LLM MOD 20 = 19
                        1      2         51     52               919        969    770       1020     1
                Lane 0 1:16 (FAS) 321:336  16001:16016 305:320   33:48   16033:16048  17:32  16017:16032 1:16 (FAS)
                Lane 1  17:32  337:352  16017:16032 1:16 (FAS)   49:64   16049:16064  33:48  16033:16048  17:32
                        ...    ...  ...   ...    ...     ...      ...  ......  ...  ...  ...   ...    ...
               Lane 18 289:304  609:624  16289:16304 273:288   1:16 (FAS)  16001:16016 305:320  16305:16320 289:304
               Lane 19 305:320  625:640  16305:16320 289:304     17:32   16017:16032 1:16 (FAS)  16001:16016 305:320
                                                                                              G.709-Y.1331(12)_FC.3


                                 Figure C.3 – Distribution of bytes from OTU4 to parallel lanes





























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