Page 1254 - 5G Basics - Core Network Aspects

2 Transport aspects

The distribution of 16-byte blocks from the sequence of OTU3 frames is illustrated in Figure C.2:

The parallel lanes can be reassembled at the sink by first recovering framing on each of the parallel lanes,
then recovering the lane identifiers and then performing lane de-skewing. Frame alignment, lane identifier
–3
recovery and multi-lane alignment should operate under 10 bit error rate conditions before error
correction. Refer to [ITU-T G.798] for the specific processing details.
The lane rotation mechanism will place the first 16 bytes of the OTU3 frame on each lane once per 4080  4
(i.e., 16320) bytes (the same as an OTU3 itself). The two LSBs of the MFAS will be the same in each FAS on a
particular lane, which allows the lane to be identified. Since the MFAS cycles through 256 distinct values,
the lanes can be de-skewed and reassembled by the receiver as long as the total skew does not exceed 127
OTU3 frame periods (approximately 385 s). The receiver must use the MFAS to identify each received
lane, as lane positions may not be preserved by the optical modules to be used for this application.
OTU4 16-byte increment distribution

Each 16-byte increment of an OTU4 frame is distributed, round robin, to each of the 20 logical lanes. On
each OTU4 frame boundary the lane assignments are rotated.

For distribution of OTU4 to twenty logical lanes, since the MFAS is not a multiple of 20, a different marking
mechanism must be used. Since the frame alignment signal is 6 bytes (48 bits) and as per [ITU-T G.798] only
32 bits must be checked for frame alignment, the third OA2 byte position will be borrowed as a logical lane
marker (LLM). For maximum skew detection range, the lane marker value will increment on successive
frames from 0-239 (240 values being the largest multiple of 20 that can be represented in 8-bits). LLM = 0
position shall be aligned with MFAS = 0 position every 3840 (the least common multiple of 240 and 256)
frame periods. The logical lane number can be recovered from this value by a modulo 20 operation.
Table C.2 and Figure C.3 illustrate how bytes of the OTU4 are distributed in 16-byte increments across the
20 logical lanes.

The pattern repeats every 320 bytes until the end of the OTU4 frame.
The following OTU4 frame will use different lane assignment according to the LLM MOD 20.

Table C.2 – Lane rotation assignments for OTU4

LLM MOD 20 Lane 0 Lane 1 ………………. Lane 18 Lane 19
0 1:16 17:32 289:304 305:320
1 305:320 1:16 273:288 289:304
:
18 33:48 49:64 1:16 17:32

19 17:32 33:48 305:320 1:16

The distribution of 16-byte blocks from the sequence of OTU4 frames is illustrated in Figure C.3.
The parallel lanes can be reassembled at the sink by first recovering framing on each of the parallel lanes,
then recovering the lane identifiers and then performing de-skewing of the lanes. Frame alignment, lane
–3
identifier recovery and multi-lane alignment should operate under 10 bit error rate conditions before
error correction. Refer to [ITU-T G.798] for specific processing details.
The lane rotation mechanism will place the first 16 bytes of the OTU4 frame on each lane once per 40804
(i.e., 16320) bytes (the same as an OTU4 itself). The "LLM MOD 20" will be the same in each FAS on a
particular lane, which allows the lane to be identified. Since the LLM cycles through 240 distinct values, the
lanes can be de-skewed and reassembled by the receiver as long as the total skew does not exceed 119
OTU4 frame periods (approximately 139 s). The receiver must use the "LLM MOD 20" to identify each
received lane, as lane positions may not be preserved by the optical modules to be used for this
application.

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