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ITU Journal on Future and Evolving Technologies, Volume 2 (2021), Issue 1




          still fewer than Reed‑Solomon’s and without recurring to  tions on an FPGA processes and simplifying the complex‑
          multiplication or RAM‑consuming tables. This amount of  ity of the Reed‑Solomon encoder/decoder design [17].
                   consumed is a trivial and negligible amount com‑  We will include then the implementation of the complete
          pared to the available          in our board.        chain OFDM Tx‑Rx on an FPGA.
          Table 5 – Parallel Hamming and Reed‑Solomon encoder/decoder re‑  REFERENCES
          sources
                                                               [1] S. Tilkioglu, “OFDM Transmitter and Receiver Im‑
                                                                           ̆
                      ECC          Resource type  Utilisation
                                                                   plementation on FPGA,” in Master Thesis disserta‑
                                                                   tion, Graduate School of Natural and Applied Sciences
             Hamming Encoder 5 × [15, 11]  LUT    30
                                       IO         130              Electronic and Communication Engineering, 2018.
             Hamming Decoder 5 × [15, 11]  LUT    50
                                       IO         130          [2] Y. J. Qazi, J. A. Malik, and S. Muhammad, “Performance
             Reed‑Solomon Encoder (64, 56)  LUT   90               Evaluation of Error Correcting Techniques for OFDM
                                      FDRE        20               Systems,” in Book, 2014.
             Reed‑Solomon Decoder (64, 56)  LUT   260
                                      FDRE        230
                                                               [3] A. Skylar et al., “Optimization of Error Correcting
          WhileourparallelHammingcode5×[15, 11]canbeimple‑         Codes in FPGA Fabric Onboard Cube Satellites,” in
          mented using only 30 LUTs for the encoders and 50 LUTs   Ph.D Thesis dissertation, Montana State University‑
          for the decoders, Reed‑Solomon code requires a higher    Bozeman Norm Asbjornson College of Engineering,
          number of blocks which are complex and uses more re‑     2019.
          sources for the Reed‑Solomon encoder/decoder up to 3×
          parallel Hamming encoder and 5×parallel Hamming de‑  [4] A. M. Cruz et al., “Low Complexity Turbo code Speci i‑
                                                                   cation for Power‑Line Communication (PLC),” in 2011
          coder. For more details, we have made the comparison     IEEE Electronics, Robotics and Automotive Mechanics
          between Hamming code and Reed‑Solomon coding based       Conference.  IEEE, 2011, pp. 349–354.
          on the aspects of memory occupation and running time in
          our work [13].                                       [5] L. M. Ionescu, C. Anton et al., “Hardware implementa‑
                                                                   tion of BCH Error‑correcting codes on a FPGA,” in In‑
          6.  CONCLUSION                                           ternational Journal of Intelligent Computing Research
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          This paper deals with the design of an Error Correct‑
          ing Code in a short‑frame OFDM communication system.  [6] S. Mahajan et al., “BER Performance of Reed‑Solomon
          In order to respond favourably to the requirements of    Code Using M‑ary FSK Modulation in AWGN Chan‑
          the low‑powered sensor network, we have analysed the     nel,” in International Journal of Advances in Science
          performance of several Error Correcting Codes (ECCs):    and Technology, vol. 3, no. 1, pp. 7–15, 2011.
          such as Hamming code and Reed‑Solomon code based     [7] V. Kavinilavu, S. Salivahanan et al., “Implementation
          on different parameters. Moreover, we have discussed
          the trade‑off between the low implementation complex‑    of Convolutional Encoder and Viterbi Decoder using
          ity (Hamming is the easiest to implement) and the high   Verilog HDL,” in International Conference on Electron‑
          error correction capacity (Reed‑Solomon being the most   ics Computer Technology, vol. 1. IEEE, 2011, pp. 297–
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          rection capacity of Hamming code, or decrease the com‑  [8] Z. He, S. Roy et al., “FPGA implementation of LDPC
          plexity cost for Reed‑Solomon code. That ’s why, we pro‑  decoders based on joint row‑column decoding algo‑
          pose a new design of parallel Hamming Coding. The par‑   rithm,” in IEEE International Symposium on Circuits
          allel Hamming Code is chosen as  ive blocks of simple    and Systems.  IEEE, 2007, pp. 1653–1656.
          Hamming Code [15, 11]. Each encoder takes 11 bytes date
          block and generate 15 byte code block to be transmitted  [9] C. H. Jones, “Communications over Aircraft Power
          on the communication channel. After an implementation    Lines,” in IEEE International Symposium on Power
          of this solution on an FPGA mock‑up, we have shown that  Line Communications and Its Applications.  IEEE,
          this parallel hamming encoder/decoder uses a few LUTs    2006, pp. 149–154.
          and has the capability of correcting up to  ive errors per  [10] V. Degardin, E. Simon et al., “On the Possibility of
          message (packet with 55 bits). The encoder and decoder   Using PLC in Aircraft,” in IEEE International Sympo‑
          coding is done in VHDL on Xilinx tool. This process is im‑  sium on Power Line Communications and Its Applica‑
          plemented on Xilinx Spartan 7 FPGA.                      tions (ISPLC).  IEEE, 2010, pp. 337–340.
          Future work will include modelling the analog part of the
          PLC channel by the Matlab toolbox Simscape [16] instead  [11] M. Shirvanimoghaddam et al., “Short Block‑length
          of the AWGN channel estimation. Moreover, we will study  Codes for Ultra‑Reliable Low Latency Communica‑
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          for the Reed‑Solomon code by removing the multiplica‑    no. 2, pp. 1–8, 2019.





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