Page 101 - ITUJournal Future and evolving technologies Volume 2 (2021), Issue 1

ITU Journal on Future and Evolving Technologies, Volume 2 (2021), Issue 1

(a)

(a)

(b)

Fig. 12 – VHDL functional simulation output of: (a) Hamming encoder
[15, 11]; (b) Hamming decoder (15, 11)

rectly.
Next, once this step has been simulated successfully in
ModelSim, we we will implement and synthesize the code
in Vivado which represent the Xilinx software for this
FPGA mock‑up.

5.3 Performance and experimental results

(b) As we have seen before, we conclude our study of the
Hamming encoder/decoder [15, 11] by synthesizing and
Fig. 11 – Design in terms of logic ports of: (a) One Hamming encoder implementing the VHDL code using Vivado. We have used
[15, 11]; (b) One Hamming decoder (15,11) a Xilinx Spartan 7 mock‑up for the implementation. Using
formation bits ( , ..., ) at the transmitter (Hamming the same code that was validated previously by ModelSim,
1
11
encoder) and then removed at the receiver (Hamming de‑ we create one project for each module (encoder and de‑
coder) which is able to detect and correct errors. coder) and we seek to verify the consumed and utilized
resources in the FPGA mock‑up.
5.2 VHDL functional simulations As we can see in Fig. 11, the synthesis was successful and
we manage to create a logic port scheme of both encoder
Next, we will create the VHDL functional simulation of the and decoder.
Hamming encoder/decoder [15, 11] module based on two We denoted by : a Look‑up table which represents
VHDL iles, one for the encoder which calculates parity a small asynchronous SRAM used to implement combina‑
bits and outputs the original message with the parity bits tional logic and by : an Input/Output Buffer.
added in speci ic positions and one for the decoder which Table 5 shows the amount of look‑up tables that are taken
recalculates the parity bits to locate the error, correct it, by our encoder and decoder. With a total of 6 + 10 = 16
and outputs the original 11 bit message. for the couple encoder/decoder, we con irm Ham‑
Therefore, we make a test bench for each ile in order ming’s code simplicity that was supposed in our analysis
to test their encoding and correction capability. In the in Section 3.
Fig. 12, we can see the simulation in ModelSim of the test Furthermore, knowing how much one Hamming en‑
benches of both the encoder and the decoder. The input coder/decoder module would consume, we can deduce
is the 2048 values that the 11 bit message can take, the that our parallel coding with ive couples of encoders/de‑
output is this same ile so our encoder [15, 11] works cor‑ coders would consume 5 × 16 = 80 , which is

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