Page 1283 - 5G Basics - Core Network Aspects

Transport aspects 2

Data in
  

D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Q 
S S S S S S S S S S S S S S S S
OTU0LL
clock
Scrambled
OTU0LL MSB of MFAS byte data out
G.709-Y.1331(12)-Amd.2(13)_FG.3

Figure G.3  Frame synchronous scrambler

The scrambler shall be reset to "FFFF" (HEX) on the most significant bit of the byte following the last
framing byte in the OTU0LL frame, i.e., the MSB of the MFAS byte. This bit, and all subsequent bits to be
scrambled shall be added modulo 2 to the output from the x position of the scrambler. The scrambler
16
shall run continuously throughout the complete OTU0LL frame. The framing bytes (FAS) of the OTU0LL
overhead shall not be scrambled.

Scrambling is performed after FEC computation and insertion into the OTU0LL signal.

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