Page 42 - First special issue on The impact of Artificial Intelligence on communication networks and services
P. 42
,78 -2851$/ ,&7 'LVFRYHULHV 9RO 0DUFK
[56] Y.-H. Chen, T. Krishna, J. S. Emer, and V. Sze, “Eye- [66] C. Zhang, P. Li, G. Sun, Y. Guan, B. Xiao, and J. Cong,
riss: An energy-efficient reconfigurable accelerator for “Optimizing fpga-based accelerator design for deep
deep convolutional neural networks,” IEEE Journal of convolutional neural networks,” in Proceedings of the
Solid-State Circuits, vol. 52, no. 1, pp. 127–138, 2017. 2015 ACM/SIGDA International Symposium on Field-
Programmable Gate Arrays. ACM, 2015, pp. 161–
[57] B. Moons, R. Uytterhoeven, W. Dehaene, and M. Ver- 170.
helst, “Envision: A 0.26-to-10 tops/w subword-
parallel dynamic-voltage-accuracy-frequency-scalable [67] N. Suda, V. Chandra, G. Dasika, A. Mohanty, Y. Ma,
convolutional neural network processor in 28nm fdsoi,” S. Vrudhula, J.-s. Seo, and Y. Cao, “Throughput-
in IEEE International Solid-State Circuits Conference optimized OpenCL-based FPGA accelerator for large-
(ISSCC), 2017, pp. 246–257. scale convolutional neural networks,” in Proceedings
of the 2016 ACM/SIGDA International Symposium on
[58] N. P. Jouppi, C. Young, N. Patil, D. Patterson,
Field-Programmable Gate Arrays. ACM, 2016, pp.
G. Agrawal, R. Bajwa, S. Bates, S. Bhatia, N. Bo-
16–25.
den, A. Borchers et al., “In-datacenter performance
analysis of a tensor processing unit,” arXiv preprint [68] Y. Chen, T. Luo, S. Liu, S. Zhang, L. He, J. Wang,
arXiv:1704.04760, 2017. L. Li, T. Chen, Z. Xu, N. Sun et al., “Dadiannao:
A machine-learning supercomputer,” in Proceedings of
[59] J. Jeddeloh and B. Keeth, “Hybrid memory cube new the 47th Annual IEEE/ACM International Symposium
dram architecture increases density and performance,”
on Microarchitecture. IEEE Computer Society, 2014,
in VLSI Technology (VLSIT), 2012 Symposium on. pp. 609–622.
IEEE, 2012, pp. 87–88.
[69] Z. Du, R. Fasthuber, T. Chen, P. Ienne, L. Li, T. Luo,
[60] M. Gao, J. Pu, X. Yang, M. Horowitz, and
X. Feng, Y. Chen, and O. Temam, “Shidiannao: Shift-
C. Kozyrakis, “Tetris: Scalable and efficient neural net-
ing vision processing closer to the sensor,” in ACM
work acceleration with 3d memory,” in Proceedings of
SIGARCH Computer Architecture News, vol. 43, no. 3.
the Twenty-Second International Conference on Archi-
ACM, 2015, pp. 92–104.
tectural Support for Programming Languages and Op-
erating Systems. ACM, 2017, pp. 751–764.
[70] D. Liu, T. Chen, S. Liu, J. Zhou, S. Zhou, O. Teman,
[61] D. Kim, J. Kung, S. Chai, S. Yalamanchili, and X. Feng, X. Zhou, and Y. Chen, “Pudiannao: A polyva-
S. Mukhopadhyay, “Neurocube: A programmable lent machine learning accelerator,” in ACM SIGARCH
Computer Architecture News, vol. 43, no. 1. ACM,
digital neuromorphic architecture with high-density
2015, pp. 369–381.
3d memory,” in Computer Architecture (ISCA), 2016
ACM/IEEE 43rd Annual International Symposium on.
[71] S. Han, H. Mao, and W. J. Dally, “Deep compres-
IEEE, 2016, pp. 380–392.
sion: Compressing deep neural networks with prun-
[62] L. Chua, “Memristor-the missing circuit element,” ing, trained quantization and huffman coding,” arXiv
IEEE Transactions on circuit theory, vol. 18, no. 5, pp. preprint arXiv:1510.00149, 2015.
507–519, 1971.
[72] A. Lavin and S. Gray, “Fast algorithms for convolu-
[63] A. Shafiee, A. Nag, N. Muralimanohar, R. Balasub- tional neural networks,” in Proceedings of the IEEE
ramonian, J. P. Strachan, M. Hu, R. S. Williams, and Conference on Computer Vision and Pattern Recogni-
V. Srikumar, “Isaac: A convolutional neural network tion, 2016, pp. 4013–4021.
accelerator with in-situ analog arithmetic in crossbars,”
in Proceedings of the 43rd International Symposium on [73] M. Mathieu, M. Henaff, and Y. LeCun, “Fast training
Computer Architecture. IEEE Press, 2016, pp. 14–26. of convolutional networks through ffts,” arXiv preprint
arXiv:1312.5851, 2013.
[64] P. Chi, S. Li, C. Xu, T. Zhang, J. Zhao, Y. Liu, Y. Wang,
and Y. Xie, “Prime: A novel processing-in-memory [74] J. Qiu, J. Wang, S. Yao, K. Guo, B. Li, E. Zhou, J. Yu,
architecture for neural network computation in reram- T. Tang, N. Xu, S. Song et al., “Going deeper with
based main memory,” in Proceedings of the 43rd Inter- embedded fpga platform for convolutional neural net-
national Symposium on Computer Architecture. IEEE work,” in Proceedings of the 2016 ACM/SIGDA Inter-
Press, 2016, pp. 27–39. national Symposium on Field-Programmable Gate Ar-
rays. ACM, 2016, pp. 26–35.
[65] S. Chakradhar, M. Sankaradas, V. Jakkula, and
S. Cadambi, “A dynamically configurable coprocessor [75] W. Liu, D. Anguelov, D. Erhan, C. Szegedy, S. Reed,
for convolutional neural networks,” in ACM SIGARCH C.-Y. Fu, and A. C. Berg, “Ssd: Single shot multibox
Computer Architecture News, vol. 38, no. 3. ACM, detector,” in European conference on computer vision.
2010, pp. 247–257. Springer, 2016, pp. 21–37.
,QWHUQDWLRQDO 7HOHFRPPXQLFDWLRQ 8QLRQ