1     General
 2     Service characteristics
        2.1     Services required from the physical medium
        2.2     Service provided to layer 2
                  2.2.1     Transmission capability
                  2.2.2     Activation/deactivation
                  2.2.3     D-channel access
                  2.2.4     Maintenance
                  2.2.5     Status indication
        2.3     Primitives between layer 1 and the other entities
 3     Modes of operation
        3.1     Point-to-point operation
        3.2     Point-to-multipoint operation
 4     Types of wiring configuration
        4.1     Point-to-point configuration
        4.2     Point-to-multipoint configuration
        4.3     Wiring polarity integrity
        4.4     Location of the interfaces
        4.5     NT and TE associated wiring
 5     Functional characteristics
        5.1     Interface functions
                  5.1.1     B-channel
                  5.1.2     Bit timing
                  5.1.3     Octet timing
                  5.1.4     Frame alignment
                  5.1.5     D-channel
                  5.1.6     D-channel access procedure
                  5.1.7     Power feeding
                  5.1.8     Deactivation
                  5.1.9     Activation
        5.2     Interchange circuits
        5.3     Connected/disconnected indication
                  5.3.1     TEs powered across the interface
                  5.3.2     TEs not powered across the interface
                  5.3.3     Indication of connection status
        5.4     Frame structure
                  5.4.1     Bit rate     
                  5.4.2     Binary organization of the frame
        5.5     Line code
        5.6     Timing considerations
 6     Interface procedures
        6.1     D-channel access procedure
                  6.1.1     Interframe (layer 2) time fill
                  6.1.2     D-echo channel
                  6.1.3     D-channel monitoring
                  6.1.4     Priority mechanism
                  6.1.5     Collision detection
                  6.1.6     Priority system
        6.2     Activation/deactivation
                  6.2.1     Definitions
                  6.2.2     Signals      
                  6.2.3     Activation/deactivation procedure for TEs
                  6.2.4     Activation/deactivation for NTs
                  6.2.5     Timer values
                  6.2.6     Activation times
                  6.2.7     Deactivation times
        6.3     Frame alignment procedures
                  6.3.1     Frame alignment procedure in the direction NT to TE
                  6.3.2     Frame alignment in the direction TE to NT
                  6.3.3     Multiframing
                  6.3.4     S-channel structuring algorithm
        6.4     Idle channel code on the B-channels
 7     Layer 1 maintenance
        7.1     Provision for operational and maintenace functions between terminal and NT1
                  7.1.1     Introduction
                  7.1.2     Test loopbacks
                  7.1.3     Codes, message durations, and detection algorithms for a Q-channel and SC1‑subchannel
                  7.1.4     Code priorities for Q-channel and SC1-subchannel
                  7.1.5     TE-to-NT direction messages (Q bits)
                  7.1.6     NT-to-TE direction messages (SC1 bits)
                  7.1.7     B-channel loopback indications (LB1I, LB2I, LB1/2I)
                  7.1.8     Loss-of-received-signal indication (LRS)
                  7.1.9     Disruptive NT Operation Indication (DOI)
 8     Electrical characteristics
        8.1     Bit rate
                  8.1.1     Nominal rate
                  8.1.2     Tolerance
        8.2     Jitter and bit-phase relationship between TE input and output
                  8.2.1     Test configurations
                  8.2.2     Timing extraction jitter
                  8.2.3     Total phase deviation input to output
        8.3     NT jitter characteristics
        8.4     Termination of the line
        8.5     Transmitter output characteristics
                  8.5.1     Transmitter output impedance
                  8.5.2     Test load impedance
                  8.5.3     Pulse shape and amplitude (binary ZERO)
                  8.5.4     Pulse unbalance
                  8.5.5     Voltage on other test loads (TE only)
                  8.5.6     Unbalance about earth
        8.6     Receiver input characteristics
                  8.6.1     Receiver input impedance
                  8.6.2     Receiver sensitivity – Noise and distortion immunity
                  8.6.3     NT receiver input delay characteristics
                  8.6.4     Unbalance about earth
        8.7     Isolation from external voltages
        8.8     Interconnecting media characteristics
        8.9     Standard ISDN basic access TE cord
       8.10     Longitudinal output voltage
       8.11     Electromagnetic compatibility (EMC)
 9     Power feeding
        9.1     Reference configuration
                  9.1.1     Functions specified at the access leads
                  9.1.2     Provision of power sources and sinks
                  9.1.3     Power feeding voltage
        9.2     Power available from NT
                  9.2.1     Power source 1 normal and restricted mode
                  9.2.2     Voltage NT from power source 1
                  9.2.3     Voltage of power source 2
                  9.2.4     Short circuit protection
        9.3     Power available at TE
                  9.3.1     Power consumption unit
                  9.3.2     Power source 1 – Phantom powering
                  9.3.3     Power source 2 – Optional third pair
        9.4     PS1 current transient
        9.5     TE power consumption
                  9.5.1     Power source 1
                  9.5.2     Power source 2
        9.6     Galvanic isolation
        9.7     Limitations on power source and sink during transient condition
                  9.7.1     Current/time limitations for TEs
                  9.7.2     Power source switchover time (PS1 or PS2)
                  9.7.3     Other TE requirements
                  9.7.4     Other power source requirements
        9.8     PS1 direct current unbalance
                  9.8.1     TE requirements
                  9.8.2     NT requirements
        9.9     Additional requirements for an auxiliary power supply (APS)
                  9.9.1     Power available from an APS
                  9.9.2     APS switch-on time
                  9.9.3     APS switch-off time
                  9.9.4     APS power consumption when off
                  9.9.5     Dynamic behaviour of APS
       9.10     Additional requirements for NT1 restricted mode source for compatibility with an APS
                 9.10.1     PS1 restricted mode back-off
                 9.10.2     PS1 restricted mode power-up
                 9.10.3     NT1 power consumption from APS normal mode
10     Interface connector contact assignments
Annex  A –Wiring configurations and round trip delay considerations used as a basis for electrical characteristics
        A.1     Introduction
        A.2     Wiring configurations
                  A.2.1     Point‑to‑multipoint
                  A.2.2     Point-to-point (Figure A.3)
Annex B – SDL representation of a possible implementation of the D-channel access
Annex C
Annex D – Test configuration
Appendix I – Testing methods
        I.1     Introduction
                  I.1.1     Basic assumptions for test
        I.2     D-channel tests
                  I.2.1     D-echo channel
                  I.2.2     D-echo channel response
        I.3     Interface procedure tests
                  I.3.1     Activation/Deactivation procedures
                  I.3.2     Timer for activation/deactivation
        I.4     TE jitter characteristics
                  I.4.1     TE jitter measurement characteristics
                  I.4.2     TE output phase offset
        I.5     Pulse shape and amplitude
                  I.5.1     Pulse shape
                  I.5.2     Pulse unbalance test
        I.6     Terminal power feeding dynamic requirements
                  I.6.1     Test of TE start-up
                  I.6.2     Current transient
                  I.6.3     Current/Time limitations for TEs
                  I.6.4     Protection against short-term interruptions
                  I.6.5     TE Behaviour at switchover
                  I.6.6     Behaviour at low input voltage
        I.7     Power source dynamic requirements
                  I.7.1     Power source type
                  I.7.2     Restricted mode requirements for type a) sources only
                  I.7.3     Normal mode requirements for type a) sources only
                  I.7.4     Restricted mode requirements for both type a) and type b) sources
                  I.7.5     Normal mode requirements for both type a) and type b) sources
                  I.7.6     Power source switchover
                  I.7.7     PS1 restricted mode power-up
        I.8     APS Dynamic requirements
                  I.8.1     APS Switch-on time
                  I.8.2     APS switch-off time
        I.9     Testing for current unbalance
Appendix II – Guidelines for implementation
       II.1     Power feeding
                 II.1.1     Introduction
                 II.1.2     Power consumption
                 II.1.3     General assumptions
                 II.1.4     Power source ripple
                 II.1.5     Dynamic behaviour of power sources and sinks
                 II.1.6     Power source design for improved performance
                 II.1.7     TE design for improved performance
       II.2     Information on activation and deactivation tables
                 II.2.1     Operation of Timer T3
                 II.2.2     Connection status