1
Scope
2 References
3 Definitions and abbreviations
3.1 Definitions
3.2 Abbreviations
4 Reference models
4.1 STU‑x functional model
4.2 User plane protocol reference model
4.3 Application models
5 Transport capacity
6 PMD layer functional
characteristics
6.1 Data mode operation
6.2 PMD activation sequence
6.3 PMD pre-activation sequence
6.4 G.994.1 pre‑activation
sequence
7 PMS-TC layer functional
characteristics
7.1 Data mode operation
7.2 PMS-TC activation
8 TPS-TC layer functional
characteristics
8.1 Payload block data structure
8.2 Data interleaving in M-pair
mode
9 Management
9.1 Management reference model
9.2 SHDSL performance primitives
9.3 SHDSL line related performance
parameters
9.4 Performance data storage
9.5 Embedded operations channel
10 Clock architecture
10.1 Reference clock architecture
10.2 Clock accuracy
10.3 Definitions of clock sources
10.4 Synchronization to clock sources
11 Electrical characteristics
11.1 Longitudinal balance
11.2 Longitudinal output voltage
11.3 Return loss
11.4 Transmit power testing
11.5 Signal transfer delay
12 Conformance testing
12.1 Micro‑interruptions
Annex A
– Regional requirements – Region 1
A.1 Scope
A.2 Test loops
A.3 Performance Tests
A.4 PSD masks
A.5 Region-specific functional
characteristics
Annex B
– Regional requirements – Region 2
B.1 Scope
B.2 Test loops
B.3 Performance testing
B.4 PSD masks
B.5 Region-specific functional
characteristics
Annex C
– Regional requirements – Region 3
Annex D
– Signal regenerator operation
D.1 Reference diagram
D.2 Start-up procedures
D.3 Symbol rates
D.4 PSD masks
Annex E
– Application-specific TPS-TC
framing
E.1 TPS-TC for clear channel data
E.2 TPS-TC for clear channel
byte-oriented data
E.3 TPS-TC for unaligned DS1 transport
E.4 TPS-TC for aligned DS1/fractional
DS1 transport
E.5 TPS-TC for European 2048 kbit/s
digital unstructured leased line (D2048U)
E.6 TPS-TC for unaligned European
2048 kbit/s digital structured leased line (D2048S)
E.7 TPS-TC for aligned European
2048 kbit/s digital structured leased line (D2048S) and fractional
E.8 TPS-TC for synchronous ISDN basic
access
E.9 TPS-TC for ATM transport
E.10 Dual-bearer TPS-TC mode
E.11 TPS-TC for PTM transport
E.12 TPS-TC for STM with a Dedicated
Signalling Channel (DSC)
E.13 TPS-TC for LAPV5 enveloped POTS or
ISDN
Annex F
– Region 1
requirements for payload data rates up to 5696 kbit/s
F.1 Scope
F.2 Data rate
F.3 Mapper
F.4 PSD masks
F.5 Crosstalk interference
requirements
F.6 Functional characteristics
Annex G
– Reserved for Region 2 requirements for data rates between 2320 kbit/s and **max rate**
Annex H
– Deactivation and warm-start procedure
H.1 Deactivation to reduced power mode
H.2 Warm-start activation
Appendix
I – Test circuit examples
I.1 Example crosstalk injection test circuit
I.2 Example coupling circuits for longitudinal balance and longitudinal
output voltage
I.3 Return loss test circuit
I.4 Transmit PSD/total power measurement test circuit
Appendix
II – Typical characteristics of cables
II.1 Typical characteristics of cables
for Annex B
Appendix
III – Signal regenerator start-up description
III.1 STU‑R initiated Start-up
III.2 STU‑C initiated start-up
III.3 SRU initiated start-up
III.4 Collisions and retrains
III.5 Diagnostic mode activation
Appendix
IV – Tabulation of Annex B noise profiles
BIBLIOGRAPHY