Table of Contents

 1     Scope          
 2     References
 3     Definitions
        3.1     Terms defined elsewhere       
        3.2     Terms defined in this Recommendation           
 4     Abbreviations and acronyms             
 5     Conventions            
 6     Use of PTP for phase/time distribution         
        6.1     High-level design requirements           
        6.2     PTP modes and options           
        6.3     Protection aspects and Alternate BMCA           
        6.4     Phase/time traceability information   
 7     ITU-T PTP profile for phase/time distribution with full timing support from the network        
 8     Security aspects     
Annex A – ITU-T PTP profile for phase/time distribution with full timing support from the network    
        A.1 Profile identification 
        A.2 PTP attribute values  
        A.3     PTP options  
        A.4     Best master clock algorithm options  
        A.5     Path delay measurement option (delay request/delay response)          
        A.6     Clock identity format
        A.7     Configuration management options  
        A.8     Security aspects          
        A.9     Other optional features of IEEE 1588  
       A.10     PTP common header flags     
Annex B – Options to establish the PTP topology with the Alternate BMCA    
Annex C – Inclusion of an external phase/time input interface in a T-BC    
Annex D – Path trace (optional)    
Annex E – Synchronization uncertain indication (optional)    
Annex F – Use of stepsRemoved to limit reference chain (optional)    
Annex G – Monitoring a PTP MASTER port by a PTP PASSIVE port (optional)    
Appendix I – Considerations on the use of transparent clock    
Appendix II – Considerations on the transmission of Delay_Req messages    
Appendix III – Considerations on the choice of the PTP Ethernet multicast destination address    
Appendix IV – Considerations on the use of priority2    
Appendix V – Description of PTP clock states and associated contents of Announce messages    
        V.1 Purpose of this appendix        
        V.2 Description of the states         
        V.3 Example of mapping between PTP port states and PTP clock states for a 3-port T-BC    
        V.4 T-GM Announce message contents based on the internal PTP clock states        
        V.5 T-BC Announce message contents based on the internal PTP clock states          
Appendix VI – Operations over link aggregation    
Appendix VII – Relationship between clockClass and holdover specification    
Appendix VIII – Considerations on a T-TSC connected to an end application    
Appendix IX – Calculation of offsetScaledLogVariance for T-GM timed by PRTC or ePRTC    
       IX.1     Observation interval and TDEV noise generation          
       IX.2     Computation of PTP variance from TDEV          
       IX.3     Computation of offsetScaledLogVariance from PTP variance   
Appendix X – Description of a T-BC extended clockClass application    
        X.1     Purpose of T-BC extended clockClass application          
        X.2     DefaultDS data set member specifications under this extended application      
Appendix XI – Considerations on native access equipment    
Appendix XII – Monitoring alternate master time information provided by a peer PTP port    
Bibliography