Table of Contents - G.8273.2/Y.1368.2 (2023) Amd. 1 (08/2024) -

1	Scope
2	References
3	Definitions
	3.1	Terms defined elsewhere
	3.2	Terms defined in this Recommendation
4	Abbreviations and acronyms
5	Conventions
6	Physical layer frequency performance requirements
	6.1	Synchronous equipment clock interfaces
	6.2	Enhanced synchronous equipment clock interfaces
7	T-BC packet layer performance requirements for full timing support from the network
	7.1	Time error noise generation
	7.2	Noise tolerance
	7.3	Noise transfer
	7.4	Transient response and holdover performance
	7.5	Interfaces
Annex A – Telecom boundary clock and telecom synchronous clock models
Annex B – Control of the phase transient due to rearrangements in the physical layer network
Annex C – Control of the phase transient due to rearrangements in the enhanced physical layer network
Appendix I – Mitigation of time error due to physical layer frequency input transients
Appendix II – Derivation of T-BC/T-TSC output transient mask due  to physical layer frequency network rearrangement
	II.1	Background on assumptions for and derivation of T-BC output phase error due to a physical layer frequency network rearrangement
	II.2	Construction and simplification of the physical layer frequency input transient limit
	II.3	T-BC output phase transient mask for the physical layer frequency network rearrangement case
	II.4	Construction and simplification of the enhanced physical layer frequency input transient limit
	II.5	T-BC output phase transient mask for the enhanced physical layer frequency network rearrangement case
Appendix III – Background to performance requirements of the T-BC/T-TSC
	III.1	Noise generation requirements
	III.2	Noise tolerance
	III.3	Noise transfer
	Page
	III.4	Holdover 
Appendix IV – Consideration on T-TSC embedded in end applications 
Appendix V – Performance estimation for cascaded media converters acting as T-BCs and for T-BC chains 
	V.1	Noise generation 
	V.2	Noise tolerance 
	V.3	Noise transfer 
	V.4	Transient response and holdover performance 
Appendix VI – Choice of frequencies for measuring noise transfer 
	VI.1	Envelope repeat frequency 
	VI.2	Choice of artefact frequency 
	VI.3	Possible frequencies 
	VI.4	Expected filter response (PTP to PTP and PTP to 1 PPS noise transfer) 
	VI.5	Expected filter response (physical layer frequency to PTP and physical layer frequency to 1 PPS noise transfer) 
Appendix VII – Synchronization IWF F-P node limits 
Appendix VIII – Measurement of relative time error between two T-BC output ports 
	VIII.1	Introduction 
	VIII.2	Definition of relative time error 
Appendix IX – PTP noise tolerance testing for T-BC and T-TSC clocks 
	IX.1	Testing set-up for PTP noise tolerance testing 
	IX.2	Time/Phase error noise model 
	IX.3	Explanation of Transients 
	IX.4	Clock output requirements 
	IX.5	Noise model parameters 
Appendix X – Derivation of T-BC/T-TSC output transient response due to long term rearrangement of physical layer frequency transport 
	X.1	Background on assumptions for and derivation of T-BC output max|TE| requirements
	X.2	Derivation of T-BC/T-TSC output max|TE| requirements 
Bibliography