Table of Contents

 1     Scope          
 2     References
 3     Definitions
        3.1     Terms defined elsewhere       
        3.2     Terms defined in this Recommendation           
 4     Abbreviations and acronyms             
 5     Conventions            
 6     Physical layer frequency performance requirements              
        6.1     Synchronous equipment clock interfaces         
        6.2     Enhanced synchronous equipment clock interfaces     
 7     T-BC packet layer performance requirements for full timing support from the network          
        7.1     Time error noise generation  
        7.2     Noise tolerance           
        7.3     Noise transfer              
        7.4     Transient response and holdover performance             
        7.5     Interfaces      
Annex A – Telecom boundary clock and telecom slave clock models    
Annex B – Control of the phase transient due to rearrangements in the physical layer network    
Appendix I – Mitigation of time error due to SyncE/SDH transients    
Appendix II – Derivation of T-BC/T-TSC output transient mask due  to SyncE/SDH rearrangement    
       II.1     Background on assumptions for and derivation of T-BC output phase error due to a SyncE/SDH rearrangement    
       II.2     T-BC output phase transient mask        
Appendix III – Background to performance requirements of the T-BC/T-TSC    
      III.1 Noise generation requirements            
      III.2 Noise tolerance            
      III.3     Noise transfer
      III.4     Holdover         
Appendix IV – Consideration on slave clocks embedded in end applications    
Appendix V – Performance estimation for cascaded media converters acting as T-BCs  and for T-BC chains    
        V.1 Noise generation       
        V.2 Noise tolerance          
        V.3     Noise transfer             
        V.4     Transient response and holdover performance             
Appendix VI – Choice of frequencies for measuring noise transfer    
       VI.1     Envelope repeat frequency   
       VI.2     Choice of artefact frequency
       VI.3     Possible frequencies
       VI.4     Expected filter response (PTP to PTP and PTP to 1PPS noise transfer)  
       VI.5     Expected filter response (SyncE-to-PTP and SyncE-to-1PPS noise transfer)        
Appendix VII – Synchronization IWF F-P node limits    
Appendix VIII – Measurement of relative time error between two T-BC output ports    
     VIII.1     Introduction
     VIII.2     Definition of relative time error           
Appendix IX – PTP noise tolerance testing for T-BC and T-TSC clocks    
       IX.1     Testing set-up for PTP noise tolerance testing
       IX.2     Time/Phase error noise model             
       IX.3     Explanation of Transients        
       IX.4     Clock output requirements    
       IX.5 Noise model parameters        
Bibliography