CONTENTS

 1     Scope
 2     References
 3     Definitions
 4     Abbreviations and Acronyms
 5     Network limits for the maximum output jitter and wander at an OTUk interface
        5.1     Network limits for jitter
        5.2     Network limits for wander
 6     Jitter and wander tolerance of network interfaces
        6.1     Jitter and wander tolerance of OTN interfaces
                  6.1.1     OTU1 jitter and wander tolerance
                  6.1.2     OTU2 jitter and wander tolerance
                  6.1.3     OTU3 jitter and wander tolerance
        6.2     Jitter and wander tolerance of CBR2G5, CBR10G, and CBR40G client interfaces
Annex A - Specification of the ODUk clock (ODC)
        A.1     Scope
        A.2     Applications
        A.3     Frequency accuracy
        A.4     Pull-in and pull-out ranges
                  A.4.1     Pull-in range
                  A.4.2     Pull-out range
        A.5     Noise generation
                  A.5.1     Jitter generation
                  A.5.2     Wander generation
        A.6     Noise tolerance
        A.7     Jitter transfer
                  A.7.1     Jitter transfer for ODCb
                  A.7.2     Jitter transfer for ODCr
                  A.7.3     Jitter transfer for ODCp
        A.8     Transient response
Appendix I - Relationship between network interface jitter requirements and input jitter tolerance
        I.1     Network interface jitter requirements
        I.2     Input jitter tolerance of network equipment
Appendix II - Effect of OTN on the distribution of synchronization via STM-N clients
       II.1     Introduction
       II.2     Provisional synchronization reference chain
       II.3     Synchronization network limit
       II.4     Variable channel memory
       II.5     Maximum buffer hysteresis
Appendix III - Hypothetical Reference Model (HRM) for 3R  regenerator jitter accumulation
Appendix IV - 3R regenerator jitter accumulation analyses
       IV.1     Introduction
       IV.2     Model 1
                 IV.2.1     Model details
                 IV.2.2     Model results
                 IV.2.3     References (for Appendix IV)
       IV.3     Model 2
                 IV.3.1     Introduction
                 IV.3.2     Structure of the equivalent building blocks in the noise simulation
       IV.4     Jitter generation of regenerators using parallel serial conversion
Appendix V - Additional background on demapper (ODCp) phase error and demapper wideband jitter generation requirements
        V.1     Introduction
        V.2     Demapper phase error
        V.3     Demapper wideband jitter generation due to gaps produced by fixed overhead in OTUk frame
Appendix VI - OTN atomic functions
       VI.1     Introduction