Table of Contents

 1     Scope          
 2     References
 3     Definitions
        3.1     Terms defined elsewhere       
        3.2     Terms defined in this Recommendation           
 4     Abbreviations and acronyms             
 5     Conventions            
 6     Introduction and applications           
 7     Structure and processes     
        7.1     FlexO-x-SC-m signal structure
        7.2     FlexO-x-DSH-m signal structure            
        7.3     FlexO-x-DO-m signal structure              
        7.4     Processing and information flow          
 8     FlexO frame  
 9     Alignment markers, PAD and FlexO overhead            
10     Mapping of OTUCn signal into n FlexO instances     
11     m×100G FlexO with staircase FEC interface group (FlexO-1-SC-m)   
       11.1     FlexO-1-SC frame structure  
       11.2     FlexO-1-SC bit rate and frame periods 
       11.3     FlexO-1-SC overhead  
       11.4     Staircase forward error correction (SC FEC) 
       11.5     FlexO-1-SC scrambling 
       11.6     FOIC1.k-SC  
12     200G FlexO with staircase FEC frame structure (FlexO-2-SC) 
       12.1     FlexO-2-SC frame structure  
       12.2     FlexO-2-SC bit rate and frame periods 
       12.3     FlexO-2-SC overhead  
       12.4     Staircase forward error correction (SC FEC) 
13     400G FlexO with staircase FEC frame structure (FlexO-4-SC-m) 
       13.1     FlexO-4-SC frame structure  
       13.2     FlexO-4-SC bit rate and frame periods 
       13.3     FlexO-4-SC overhead  
       13.4     Staircase forward error correction (SC FEC) 
14     FlexO-x-D<fec> 
       14.1     FlexO-x-D<fec> frame and multi-frame structures 
       14.2     FlexO-x-D<fec> Overhead  
15     FlexO-x-DSH  
       15.1     FlexO-x-DSH multi-frame and super-frame structures
       15.2     FlexO-x-DSH bit rates and frame periods 
       15.3     Overhead  
       15.4     Mapping of FlexO-x-SC client into FlexO-x-DSH payload           
       15.5     FOICx.k-DSH  
16     FlexO-x-DO  
       16.1     FlexO-x-DO multi-frame and super-frame structures 
       16.2     FlexO-x-DO bit rates and frame periods 
       16.3     Overhead  
       16.4     Mapping of FlexO-x client into FlexO-x-DO payload  
       16.5     FOICx.k-DO  
Annex A – Forward error correction using 512 × 510 staircase codes    
Annex B – Adaptation of 512 × 510 staircase codes to 100G FlexO-1-SC FEC    
        B.1     100G FlexO-1-SC bit and SC FEC specific base blocks mapping relationship  
        B.2     100G FlexO-1-SC transmitter and receiver SC FEC processing  
Annex C – Adaptation of 512 × 510 staircase codes to 200G|400G FlexO-x-SC FEC    
        C.1     200G|400G FlexO-x-SC bit and SC FEC specific base blocks mapping relationship  
        C.2     200G|400G FlexO-x-SC transmitter and receiver SC FEC processing      
Annex D – Forward error correction using 10976 × 128 Hamming soft decision codes    
        D.1     Forward error correction code  
Annex E – Forward error correction using extended BCH(256,239) soft decision code    
        E.1     Forward error correction code  
Annex F – Multiplexing OTUCni signals into payload of n FlexO instances    
        F.1     Distributing OTUCni and combining OTUC instances 
        F.2     FlexO frame and 4-frame multi-frame payload structure  
        F.3     FlexO client mapping specific overhead  
        F.4     Mapping of OTUCni into ni FlexO frames 
Annex G – FlexO-x-D<fec> TS, PS and MFAS overhead values    
        G.1     FlexO-x-DSH and FlexO-x-DO TS, PS and MFAS overhead values 
Appendix I – Example applications    
Appendix II – Error correction capability of the (128,119) Hamming soft decision code combined with the 512 × 510 staircase code    
Appendix III – Error correction capability of a soft decision decoder for OFEC    
Appendix IV – FlexO-x-DO related equation illustrations and implementation considerations    
       IV.1     Introduction  
       IV.2     Illustration of equation 16-1 
       IV.3     Illustration of equations 16-2 and 16-3 
       IV.4     Illustration of equation 16-4 
       IV.5     Illustration of bit ordering in eUi, Wi, Vi and Ii
Appendix V – Generic principles of forward error correction using blockwise-recursively-encoded open FEC    
        V.1     Open FEC codes: Specifications and basic properties 
        V.2     Permutation function  
        V.3     Decoding an open forward error correction code  
Bibliography