1 Scope
2 References
3 Definitions
4 Abbreviations and acronyms
5 Conventions
6 Description of the model
6.1 Model overview
6.2 Network topology
6.3 Models of network elements
6.4 Interfering stream files
6.5 Simulation inputs
6.6 Simulation outputs
6.7 Packet scheduling algorithm
7 IP network impairment-level requirements
7.1 Service test profiles
7.2 Impairment combination standard test cases
8 Using the network model
8.1 Using the simulator
8.2 Using a real-time hardware emulator
8.3 Hardware emulator considerations
8.4 Advanced uses of the network model
Annex A – Description of discrete event simulator
A.1 Simulator overview
A.2 Directory structure
A.3 Building the simulator
A.4 Base CORE2LAN model
A.5 Simulator input data
A.6 Running the simulation with convenience scripts
A.7 Simulator output
A.8 Plotting results
A.9 Simulator internal conventions
A.10 Simulator objects for network elements
A.11 Simulator input and output objects
A.12 Other base classes
A.13 Simulator objects for discrete event simulation
A.14 Numbering conventions in the top level simulator (CORE2LAN.cpp)
A.15 File list
A.16 Common TCL file
Annex B – C++ source code of the discrete event simulator
Annex C – Packet capture files of interfering traffic
Annex D – Simulator output
Annex E – Simulation results summary
Annex F – Electronic attachment
Bibliography