CONTENTS

Policy on Intellectual Property Right (IPR)
Annex 1  Interfaces for video signals with pixel arrays of 1 920 × 1 080, the frame frequencies up to 60 Hz and the bit depths up to 10 bit conforming to Recommendations ITU-R BT.709 and ITU-R BT.2100
 1     Digital representation
        1.1     Coding characteristics
 2     Digital interface
        2.1     Serial video data
        2.2     Video timing relationship with analogue waveform
        2.3     Video timing reference codes SAV and EAV
        2.4     Ancillary data
        2.5     Data words during blanking
 3     Bit-parallel interface
 4     Bit-serial interface
        4.1     Data format
                  4.1.1     Video data
                  4.1.2     Video timing reference codes
                  4.1.3     Interface line number data
                  4.1.4     Error detection codes
                  4.1.5     Ancillary data
                  4.1.6     Blanking data
        4.2     Transmission format
                  4.2.1     Word-multiplexing
                  4.2.2     Serializing
                  4.2.3     Channel coding
                  4.2.4     Serial clock
                  4.2.5     Bit-serial digital check field
                  4.2.6     Payload identifier
        4.3     Coaxial cable interfaces
                  4.3.1     Line driver characteristics (source)
                  4.3.2     Line receiver characteristics (destination)
                  4.3.3     Transmission line characteristics
                  4.3.4     Connector
        4.4     Optical fibre interfaces
        4.5     Bit-serial interface for 60/P and 50/P dual-link operation
                  4.5.1     Source sample numbering
                  4.5.2     Interface data streams and multiplex structure
                  4.5.3     Timing reference signals and line numbers
                  4.5.4     Signal timing considerations
                  4.5.5     Link A and link B identification
                  4.5.6     Ancillary data
                  4.5.7     Audio data
                  4.5.8     Time code
        4.6     Single link 3 Gbit/s mapping – Dual link source
                  4.6.1     Single link 3 Gbit/s payload identifier (Dual link source)
        4.7     Applications of the dual-link bit-serial digital interface
        4.8     Applications of a single 3Gbit/s link carrying data formatted on two 1.5 Gbit/s interfaces
Attachment 1 to Annex 1  Applications of the dual-link high-definition serial digital interface
 1     4:4:4 (R′G′B′) and 4:4:4:4 (R′G′B′ + A or D) 10-bit signals of 30/P, 30/PsF, 60/I, 25/P, 25/PsF, 50/I, 24/P and 24/PsF systems
        1.1     Source sample numbering
        1.2     Interface data streams
        1.3     Multiplex structure
        1.4     Auxiliary signal
 2     4:4:4 (R′G′B′) 12-bit signals of 30/P, 30/PsF, 60/I, 25/P, 25/PsF, 50/I, 24/P and 24/PsF systems
        2.1     Source sample numbering
        2.2     Interface data streams
        2.3     R′G′B′:0-1 onto first channel of link B data mapping
        2.4     Multiplex structure
 3     4:2:2 (YCBCR) 12-bit signals of 30/P, 30/PsF, 60/I, 25/P, 25/PsF, 50/I, 24/P and 24/PsF systems
        3.1     Source sample numbering
        3.2     Interface data streams
        3.3     YCBCR:0-1 and Y:0-1 onto first channel of link B data mapping
        3.4     Multiplex structure
        3.5     Auxiliary signal
 4     4:4:4 (YCBCR), 4:4:4:4 (YCBCR + A or D) 10-bit signals of 30/P, 30/PsF, 60/I, 25/P, 25/PsF, 50/I, 24/P and 24/PsF systems
        4.1     Source sample numbering
        4.2     Interface data streams
        4.3     Multiplex structure
        4.4     Auxiliary signal
 5     4:4:4 (YCBCR) 12-bit signals of 30/P, 30/PsF, 60/I, 25/P, 25/PsF, 50/I, 24/P and 24/PsF systems
        5.1     Source sample numbering
        5.2     Interface data streams
        5.3     Multiplex structure
        5.4     Additionally supported picture payload values
Attachment 2 to Annex 1  Applications of the single link 3 Gbit/s high definition serial digital interface 1.5 Gbit/s dual link to single link 3 Gbit/s mapping
 1     Dual-link source
        1.1     Data mapping
        1.2     Payload identifier
Annex 2  Bit-serial digital checkfield for use in the high-definition digital interfaces
 1     Scope
 2     General considerations
 3     Checkfield data
 4     Serial digital interface (SDI) checkfield