0     Introduction
        0.1     General
        0.2     Elements
        0.3     Basic system structure
 1     Physical layer – Characteristics of the signalling terminal/physical circuit interface
 2     Link layer procedures between signalling terminals
        2.1     Scope and field of application
        2.2     Frame structure
        2.3     Elements of procedures
        2.4     Description of the procedures
        2.5     Multilink procedures (MLP)
 3     Packet layer procedures between signalling terminals
        3.0     General principles
        3.1     Procedures for virtual call set-up and clearing
        3.2     Procedures for permanent virtual circuit service
        3.3     Procedure for data and interrupt transfer
        3.4     Procedures for flow control and for reset
        3.5     Procedure for restart
        3.6     Relationship between layers
 4     Packet formats for virtual calls and permanent virtual circuits
        4.1     General
        4.2     Call set-up and clearing packets
        4.3     Data and interrupt packets
        4.4     Flow control and reset packets
        4.5     Restart packets
 5     Procedures and formats for user facilities and network utilities
        5.1     Description of optional user facilities
        5.2     Formats for optional user facilities
        5.3     Procedures for network utilities
        5.4     Formats for network utilities
Annex A – Definition of symbols for Annexes B, C and D
        A.1     General
        A.2     Symbol definition of the state diagrams
        A.3     Order definition of the state diagrams
        A.4     Symbol definition of the action tables
Annex B – State diagrams for the packet layer interface between STEs for normal cases
Annex C – Actions taken by the STE on receipt of packets in a given state of the packet layer X/Y interface
Annex D – Actions taken by the STE on time-outs in the packet layer
Annex E – Coding of network generated diagnostic fields in X.75 clear, reset and restart packets
Annex F – Association of error conditions with cause and diagnostic codes
Appendix I – Examples of multilink resetting procedures
        I.1     Introduction
        I.2     MLP reset initiated by a single STE
        I.3     MLP reset initiated by both STEs simultaneously
Appendix II – Additional information on data signalling rates higher than 64 kbit/s
       II.1     Use of time slot 0 to 2 Mbit/s links
       II.2     Guidelines for data signalling rates higher than 64 kbit/s in order to support high throughput
Appendix  III – Guidelines for transmission over channels with long round trip delay and/or transmission rates higher than 64 kbit/s
      III.1     Preamble
      III.2     Common guidelines
      III.3     Guidelines for channels with long round trip delays operating at 64 kbit/s
      III.4     Guidelines for circuits operating at 1920 kbit/s
Appendix IV – Examples of the use of multi-selective reject option