1 Scope
2
References
3
Definitions
4
Abbreviations
5
Line signals
5.1 Data signalling rates
5.2 Symbol rates
5.3 Carrier frequencies
5.4 Pre-emphasis
6
DTE interfaces
6.1 Synchronous
interfacing (primary channel only)
6.2 Asynchronous character-mode interfacing
6.3 Half-duplex mode interfacing
6.4 Electrical characteristics of interchange circuits
6.5 Fault condition on interchange circuits
6.6 Thresholds and response times of Circuit 109
7
Scrambler
8
Framing
8.1 Overview
8.2 Mapping frame switching
8.3 Multiplexing of primary and auxiliary channel bits
9
Encoder
9.1 Signal constellations
9.2 Mapping parameters
9.3 Parser
9.4 Shell mapper
9.5 Differential encoder
9.6 Mapper, precoder and trellis encoder
9.7 Non-linear encoder
10 Start-up signals and sequences
10.1 Signals and sequences used in duplex operation
10.2 Signals and sequences used in half-duplex operation
11 Duplex operating procedures
11.1 Phase 1 – Network interaction
11.2 Phase 2 – Probing/ranging
11.3 Phase 3 – Equalizer and echo canceller training
11.4 Phase 4 – Final training
11.5 Retrains
11.6 Rate renegotiation
11.7 Cleardown
11.8 Two-wire leased line operation
12 Half-duplex operating procedures
12.1 Phase 1 – Network interaction
12.2 Phase 2 – Probing
12.3 Phase 3 – Primary channel equalizer training
12.4 Control channel start-up
12.5 Primary channel resynchronization procedure
12.6 Control channel resynchronization procedure
12.7 Primary channel retrains
12.8 Control channel retrains
13 Testing facilities
14 Glossary
14.1 Variables and Parameters used in Data mode (clauses 5 to 9)
Annex A – V.34 modem control channel procedures
A.1 Introduction
A.2 MP sequences for modem control channel compatibility
A.3 Auxiliary channel protocol for modem control
A.4 Items for further study