1     Scope
 2     Normative references
 3     Definitions
 4     Abbreviations and symbols
        4.1     Arithmetic operators
        4.2     Logical operators
        4.3     Relational operators
        4.4     Bitwise operators
        4.5     Assignment
        4.6     Mnemonics
        4.7     Constants
 5     Conventions
        5.1     Method of describing bitstream syntax
        5.2     Definition of functions
        5.3     Reserved, forbidden and marker_bit
        5.4     Arithmetic precision
 6     Video bitstream syntax and semantics
        6.1     Structure of coded video data
        6.2     Video bitstream syntax
        6.3     Video bitstream semantics
 7     The video decoding process
        7.1     Higher syntactic structures
        7.2     Variable length decoding
        7.3     Inverse scan
        7.4     Inverse quantisation
        7.5     Inverse DCT
        7.6     Motion compensation
        7.7     Spatial scalability
        7.8     SNR scalability
        7.9     Temporal scalability
       7.10     Data partitioning
       7.11     Hybrid scalability
       7.12     Output of the decoding process
 8     Profiles and levels
        8.1     ISO/IEC 11172-2 compatibility
        8.2     Relationship between defined profiles
        8.3     Relationship between defined levels
        8.4     Scalable layers
        8.5     Parameter values for defined profiles, levels and layers
        8.6     Compatibility requirements on decoders
 9     Registration of Copyright Identifiers
        9.1     General
        9.2     Implementation of a Registration Authority (RA)
Annex A – Inverse discrete transform
Annex B – Variable length code tables
        B.1     Macroblock addressing
        B.2     Macroblock type
        B.3     Macroblock pattern
        B.4     Motion vectors
        B.5     DCT coefficients
Annex C – Video buffering verifier
Annex D – Features supported by the algorithm
        D.1     Overview
        D.2     Video formats
        D.3     Picture quality
        D.4     Data rate control
        D.5     Low delay mode
        D.6     Random access/channel hopping
        D.7     Scalability
        D.8     Compatibility
        D.9     Differences between this Specification and ISO/IEC 11172-2
       D.10     Complexity
       D.11     Editing encoded bitstreams
       D.12     Trick modes
       D.13     Error resilience
       D.14     Concatenated sequences
Annex E – Profile and level restrictions
        E.1     Syntax element restrictions in profiles
        E.2     Permissible layer combinations
Annex F – Bibliography
Annex G – Registration Procedure
        G.1     Procedure for the request of a Registered Identifier (RID)
        G.2     Responsibilities of the Registration Authority
        G.3     Responsibilities of parties requesting an RID
        G.4     Appeal procedure for denied applications
Annex H – Registration Application Form
        H.1     Contact information of organization requesting a Registered Identifier (RID)
        H.2     Statement of an intention to apply the assigned RID
        H.3     Date of intended implementation of the RID
        H.4     Authorized representative
        H.5     For official use only of the Registration Authority
Annex J – 4:2:2 Profile test results
        J.1     Introduction