1 Scope
2 References
3 Definitions
4 Abbreviations
5 Network limits for jitter and wander at traffic interfaces
5.1 Jitter limits
5.2 Wander limits
5.2.1 Synchronous 1544 kbit/s network interface
5.2.2 Synchronous 44 736 kbit/s network interface
5.3 Phase transients
6 Network limits for jitter and wander at synchronization interfaces
6.1 Network limits for jitter
6.2 Network limits for wander
6.2.1 Primary Reference Clock (PRC) output
6.2.2 1544 kbit/s reference interface
7 Tolerance of jitter and wander at network interfaces
7.1 Basic specification philosophy
7.2 Jitter and wander tolerance of traffic input ports
7.2.1 1544 kbit/s input jitter and wander tolerance
7.2.2 6312 kbit/s input jitter and wander tolerance
7.2.3 32 064 kbit/s input jitter and wander tolerance
7.2.4 44 736 kbit/s input jitter and wander tolerance
7.2.5 97 728 kbit/s input jitter and wander tolerance
7.3 Jitter and wander tolerance of clock input ports
Annex A – Wander reference models and wander budgets
A.1 1544 kbit/s wander accumulation
A.1.1 1544 kbit/s wander accumulation and slip simulation model
assumptions
A.2 44 736 kbit/s wander accumulation