1
Scope
2 References
3 Terms and definitions
4 Acronyms and abbreviations
5 Conventions
6 Basic Multiplexing principles
6.1 Multiplexing structure
6.2 Basic frame structure
6.2.1 Section overhead
6.2.2 Administrative Unit pointers
6.2.3 Administrative Units in the STM-N
6.2.4 Maintenance signals
6.3 Hierarchical bit rates
6.4 Interconnection of STM-Ns
6.5 Scrambling
6.6 Physical specification of the NNI
7 Multiplexing method
7.1 Multiplexing of Administrative
Units into STM-N
7.1.1 Multiplexing of Administrative Unit Groups (AUGs) into STM-N
7.1.2 Multiplexing of an AU-4 via AUG-1
7.1.3 Multiplexing of AU-3s via AUG-1
7.1.4 Multiplexing of AU-3 into STM-0
7.2 Multiplexing of Tributary Units into
VC-4 and VC-3
7.2.1 Multiplexing of Tributary Unit Group-3s (TUG-3s) into a VC-4
7.2.2 Multiplexing of a TU-3 via TUG-3
7.2.3 Multiplexing of TUG-2s via a TUG-3
7.2.4 Multiplexing of TUG-2s into a VC-3
7.2.5 Multiplexing of a TU-2 via TUG-2s
7.2.6 Multiplexing of TU-1s via TUG-2s
7.3 AU-n/TU-n numbering scheme
7.3.1 Numbering of AU-ns (VC‑ns) in a STM-256
7.3.2 Numbering of AU-ns (VC‑ns) in a STM-64
7.3.3 Numbering of AU-ns (VC‑ns) in an STM-16
7.3.4 Numbering of AU‑ns (VC‑ns) in an STM-4
7.3.5 Numbering of AU‑4 (VC‑4) in an STM‑1 signal
7.3.6 Numbering of AU‑3 (VC‑3) in an STM‑0 signal
7.3.7 Numbering of TU-3s in a VC-4
7.3.8 Numbering of TU-2s in a VC-4
7.3.9 Numbering of TU-12s in a VC-4
7.3.10 Numbering of TU-11s in a VC-4
7.3.11 Numbering of TU-2s in a VC-3
7.3.12 Numbering of TU-12s in a VC-3
7.3.13 Numbering of TU-11s in a VC-3
8
Pointers
8.1 AU-n pointer
8.1.1 AU-n pointer location
8.1.2 AU-n pointer value
8.1.3 Frequency justification
8.1.4 New Data Flag (NDF)
8.1.5 Pointer
generation
8.1.6 Pointer interpretation
8.1.7 AU-4 concatenation
8.2 TU-3 pointer
8.2.1 TU-3 pointer location
8.2.2 TU-3 pointer value
8.2.3 Frequency justification
8.2.4 New Data Flag (NDF)
8.2.5 Pointer generation
8.2.6 Pointer interpretation
8.3 TU-2/TU-1 pointer
8.3.1 TU-2/TU-1 pointer location
8.3.2 TU-2/TU-1 pointer value
8.3.3 TU-2/TU-1 frequency justification
8.3.4 New Data Flag (NDF)
8.3.5 TU-2/TU-1 pointer generation and interpretation
8.3.6 TU-2 concatenation
8.3.7 TU-2/TU-1 sizes
8.3.8 TU-2/TU-1 multiframe indication byte
9 Overhead bytes description
9.1 Types of overhead
9.1.1 SOH
9.1.2 Virtual Container POH
9.2 SOH description
9.2.1 SOH bytes location
9.2.2 SOH bytes description
9.2.3 Reduced SOH functionalities interface
9.2.4 Forward Error Correction: P1, Q1
9.3 POH descriptions
9.3.1 VC-4-Xc/VC-4/VC-3 POH
9.3.2 VC-2/VC-1 POH
10 Mapping of tributaries into VC-n
10.1 Mapping of G.702 type signals
10.1.1 Mapping into VC-4
10.1.2 Mapping into VC-3
10.1.3 Mapping into VC-2
10.1.4 Mapping into VC-12
10.1.5 Mapping into VC-11
10.1.6 VC-11 to VC-12 conversion for
transport by a TU-12
10.2 Mapping of ATM cells
10.2.1 Mapping into VC-4-Xc/VC-4-Xv
10.2.2 Mapping into VC-4/VC-3
10.2.3 Mapping into VC-2-Xc/VC‑2‑Xv
10.2.4 Mapping into VC-2
10.2.5 Mapping into VC-12/VC-11
10.3 Mapping of HDLC framed signals
10.4 Mapping of DQDB into VC-4
10.5 Asynchronous mapping for FDDI at 125 000 kbit/s into VC-4
11 VC concatenation
11.1 Contiguous concatenation of X VC-4s (VC-4-Xc, X = 4, 16, 64,
256)
11.2 Virtual concatenation of X VC-3/4s (VC-3/4-Xv, X = 1 ... 256)
11.3 Contiguous concatenation of X VC-2s in a higher order VC-3
(VC-2-Xc, X = 1 … 7)
11.4 Virtual concatenation of X VC-2/1s
Annex A – Forward Error Correction for STM-64, and
STM-256
A.1 Network reference model
A.2 The FEC function
A.2.1 Code type and
parameters
A.2.2 FEC encoder description and algorithm
A.2.3 Encoder and decoder locations
A.2.4 FEC delay characteristic
A.2.5 SDH and FEC check bits not included in
FEC coding
A.3 Mapping into the SDH frame
A.3.1 Location of the information bits
A.3.2 Location of in-band FEC parity
A.3.3 Location of status/control bits
A.3.4 FEC Status Indication (FSI)
A.3.5 B1 calculation at encoder and decoder
A.3.6 B2 calculation at encoder and Decoder
A.4 In-band FEC regenerator functions
A.4.1 Regenerators
not supporting in-band FEC
A.4.2 Regenerators passing in-band FEC
transparently without error correction
A.4.3 Regenerators with error correction
A.5 Performance monitoring
A.5.1 FEC correctable error count
A.5.2 FEC uncorrectable error count
A.5.3 Error count after FEC decoding
A.6 FEC activation and deactivation
A.6.1 FEC Operational States
A.6.2 FEC Status Indication (FSI)
A.6.3 MS-AIS interaction with FEC
A.7 Performance of in-band FEC
Annex
B – CRC-7 polynomial
algorithm
B.1 Multiplication/division process
B.2 Encoding procedure
B.3 Decoding procedure
Annex
C – VC-4-Xc/VC-4/VC-3 Tandem Connection Monitoring protocol:
Option 1
C.1 Tandem Connection Overhead – Byte location
C.2 Definitions
C.3 Tandem Connection bundling
C.3.1 Bundling of VC-3s within an STM-1
C.3.2 Bundling of VC-3s within an STM-N
(N>1)
C.3.3 Tandem Connection Bundle Contents
C.3.4 Tandem Connection bundles in higher rate
signals
C.4 Incoming Error Count (IEC)
C.5 B3 Compensation
C.6 Data link
C.6.1 Format of the LAPD messages
C.6.2 Tandem Connection Trace, Idle Signal, and
Test Signal Identification Messages
C.6.3 The far-end performance report message
C.6.4 Special carrier applications
C.7 Treatment of Incoming Signal
Failures
C.7.1 Signal failures before the Tandem Connection
C.7.2 Signal failures within the Tandem Connection
C.8 Tandem Connection Idle Signal
C.9 Tandem Connection Test Signal
Annex D – VC-4-Xc/VC-4/VC-3 Tandem Connection Monitoring
protocol: Option 2
D.1 N1 byte structure
D.2 TCM functionality at the Tandem
Connection source
D.3 TCM functionality at the Tandem
Connection sink
D.4 BIP-8 compensation
Annex E – VC-2/VC-1 Tandem Connection Monitoring
protocol
E.1 N2 byte structure
E.2 TCM functionality at the Tandem
Connection source
E.3 TCM functionality at the Tandem
Connection sink
E.4 BIP-2 compensation
Appendix I –
Relationship between TU-2 address and location of columns within a VC-4
Appendix II –
Relationship between TU-12 address and location of columns within a VC‑4
Appendix III – Relationship between TU-11 address and
location of columns within a VC-4
Appendix IV – Relationship between TU-2
address and location of columns within a VC‑3
Appendix V – Relationship between TU-12
address and location of columns within a VC‑3
Appendix VI –
Relationship between TU-11 address and location of columns within a VC-3
Appendix VII – Enhanced Remote Defect Indication
(RDI)
Appendix VIII – Unexpected behaviour, dependence of
TC Monitoring on the incoming signal
Appendix IX – Forward Error Correction for STM-16
Appendix X – Performance of in-band FEC
Appendix XI – Bibliography