1 Scope
2
Introduction
3
Definitions
4
General Description of the Digital Parallel Interface
4.1 Logical Description
4.2 Master Clock and Reset
4.3 Timing, Timeslots and Capacity
4.4 Reset procedure
5
Hardware implementation
5.1 Connector type, pin assignment and cabling
5.2 Line drivers and receiver termination
5.3 Distributed multiplexer
5.4 Signal delays within devices
Annex A – DPI implementation using TTL logic integrated circuits
Annex B – Data formats
B.1 Time signals
B.2 Coded bitstream
Annex C – Rules for codec implementation
Annex D – Example host laboratory test configurations
Appendix I – The ITU-T 8 kbit/s speech codec test parallel interface
I.1 Specialisation of the interface
I.2 Data formats
References